Publicaciones


 

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

 

Resumen. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.

Autores. Magali Estrada Del Cueto
Revista. Solid-State Electronics
https://doi.org/10.1016/j.sse.2024.108865

Print
CONTÁCTENOS

Logo Cinvestav

Av. Instituto Politécnico Nacional 2508
Col. San Pedro Zacatenco, Alcaldía Gustavo A. Madero
Ciudad de México, C.P. 07360
Apartado Postal: 14-740, 07000 Ciudad de México

Tel. +52 (55) 5747 3800

Cinvestav © 2024
23/09/2024 02:20:25 p. m.